1. Field of the Invention
The present invention relates to video data compression systems, and more specifically, to a code table apparatus of a variable length decoder (VLD) in a video data compression system.
2. Description of the Prior Art
The main technique utilized in a data compression system is variable length coding (VLC) which transforms data into codes of variable lengths by statistical methods. That is, the data that appears more frequently is transformed into a shorter code which requires less memory capacity and shorter transmission time, thus reducing the data load of a communication medium. In order to decode or recover the codes with variable lengths into their original format, a VLD is necessary in a data compression system. Therefore, improving the operational speed of the VLD has become an important issue in high performance video systems, such as digitized high definition television (HDTV).
The variable length codes in a video system are generally generated by a discrete cosine transform (DCT). Therefore, a coefficient table called a DCT coefficient table is necessary in the VLD to recover the variable length codes into their original forms. In the past, a number of VLD structures have been disclosed, for example, U.S. Pat. Nos. 4,177,456, 5,032,838, 5,055,841, and 5,245,338. The subject matter of these U.S. Patents is incorporated herein by reference as if fully set forth herein. One of these VLD structures, illustrated in FIG. 1 (Prior Art), includes a barrel shifter 15, a DCT coefficient table 17 and a multiplexer 19. The input data of barrel shifter 15 is a data stream of successive codes with variable lengths. These codes are shifted, separated and then sequentially sent to DCT coefficient table 17 where each of the codes is decoded into a level and a length code. The level code represents the original data format and the length code stands for the length of the input code. Therefore, the length code has to be sent back to barrel shifter 15 as reference data for code shifting and separation.
Since each input code of DCT coefficient table 17 consists of a code word portion and a sign bit, DCT coefficient table 17 of a conventional VLD structure is generally separated into three portions for generating levels of positive codes, levels of negative codes and the length codes, respectively. A schematic diagram of DCT coefficient table 17 is depicted in FIG. 2. For example, DCT coefficient table 17 receives an input code "xxx . . . xs" from barrel shifter 15, wherein the front bits "xxx . . . x" are the code word portion and the last bit "s" is the sign bit. The input code "xxx . . . xs" will be directly decoded in positive level portion 11 or negative level portion 12 of DCT coefficient table 17 to generate a level code, and then output through the selection of multiplexer 19. At the same time, length code portion 13 of DCT coefficient table 17 generates a length code to barrel shifter 15 by calculating the bit number of the input code "xxx . . . xs".
Since the aforementioned VLD structure generates the level codes by two independent portions 11 and 12 in DCT coefficient table 17, the capacity of these portions must be very large when some of the codes have very long word lengths. For example, in order to satisfy the requirements of the motion picture experts group I (MPEG I) or MPEG II video standard, the VLD requires a DCT coefficient table which can decode at least 114 codes, and their code length may be as long as 17 bits. Therefore, the dimension of the VLD is dominated by DCT coefficient table 17. That is, if the VLD must be minimized so that the video system can be as compact as possible, the dimensions of DCT coefficient table should be reduced first.
On the other hand, since DCT coefficient table 17 of a convention VLD is provided by a programmable logic array (PLA), the larger the dimension of the PLA is, the longer operational time delay it will take. Since DCT coefficient table 17 requires a large capacity, the PLA dimensions are generally too large to provide high speed operation. Even though some VLD structures utilize read-only-memory devices to replace the PLA as DCT coefficient table, the vast space occupied by the ROM devices does not allow satisfactory minimization of the VLD. This means that the operating efficiency of the conventional VLD must be improved and its dimensions must be reduced by changing the decoding strategy of the DCT coefficient table.
It is also observed that positive level portion 11 and negative level portion 12 of the DCT coefficient table in the conventional VLD generate the same level code when the input codes have the same code words but different sign bits. That is, the two level portions have identical structures except for the circuit that decodes the sign bit. Obviously, the conventional VLD structure wastes a lot of space in the designation of the DCT coefficient table. Therefore, if the code word and sign bit of an input code can be processed separately, the dimensions of the DCT coefficient table for generating the level code and length code can be reduced to one half of that of a conventional VLD. This decoding strategy of the DCT coefficient table may also greatly improve the performance of the VLD.